While testing SMMBs new actuator under load, I kept getting faults from overvoltage that I had not anticipated.  The firmware only samples voltage once per control cycle, and while that plot did look very interesting, it probably wasn’t representative.  I wired up the scope to be able to sample the voltage and FET control signals during operation and sure enough, the voltage ripple was way higher than I had predicted based on the original design.  Even at only 30A phase current, the voltage ripple on the main power bus was 4.2V.  Note that this was with a nominal operating voltage of only 13V!  I had been trying to operate at 40A, for which it must have only been worse.

When I originally laid out the board, I used approximately the same bulk capacitance as Ben K. had in his third revision board; my r2 board contained 6x 22uF 35V MLCC (multi-layer ceramic capacitors) from TDK.  However, the voltage ripple observed in the plots was consistent with a much lower overall bulk capacitance.

And now begins another self-education session.  I had always assumed that modern MLCC ceramic capacitors were made of magic pixie dust and had somehow managed to achieve near capacity parity with electrolytic capacitors with no real downsides.  However, after looking into it, I found that in fact, the capacitance of a MLCC capacitor needs to be derated by the DC voltage applied to it.  The derating curve can be quite significant.  For the capacitors I had chosen, at 12V DC bias, the actual capacitance was only 20% of the top line value!  :theresyerproblem:

Fortunately TDK has a handy feature on their website which lets you sort capacitors based on their effective capacitance at any DC operating point.  I found some 10uF options that have about a 20% higher effective capacitance than the 22uF I had selected previously, and in the next revision of the control board I will just need to add a lot more of them.  In the meantime, I’ve double stacked up capacitors to get closer to something reasonable, and increased the switching frequency to 60kHz from 40kHz.  Here’s a plot of 30A when I was testing it at 80kHz, which shows a much more manageable 0.6V ripple.  Hopefully that can be reduced even further with a bit more capacitance in the next revision.